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Patent Searching and Data


Title:
CACHE MEMORY BANK CONTROLLER
Document Type and Number:
Japanese Patent JPH1083349
Kind Code:
A
Abstract:

To shorten the time needed for task switching by selecting one of cache memory banks as a selected cache memory bank associatively with a choice of a selected register bank.

A bank selecting register 7 and a selector 8 constitute a register bank selecting means A and a cache memory 9 refers to a memory word only from one cache bank indicated by the bank selecting register 7. Further, each cache bank of a cache memory 9 is composed of a tag memory and a data memory. When a task is switched, the task number of a switching destination is set in the bank selecting register 7 and then the task is switched to register banks 3 to 6 having the same number with the task number and a cache bank according to the decoding result of the value of the bank selecting register 7.


Inventors:
FUKUDA MASAHIRO
Application Number:
JP23822996A
Publication Date:
March 31, 1998
Filing Date:
September 09, 1996
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G06F9/46; G06F9/34; G06F9/48; G06F12/08; (IPC1-7): G06F12/08; G06F9/46; G06F12/08
Attorney, Agent or Firm:
Masatake Shiga