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Patent Searching and Data


Title:
CACHE MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS61241853
Kind Code:
A
Abstract:

PURPOSE: To improve the hit ratio of a secondary cache memory by storing a send-out block to the secondary cache memory at a time point when a block registered to the primary cache memory is sent out.

CONSTITUTION: The read request data is transferred to a processor 1 from a primary cache memory 2 in case said request data is stored in a block on the memory 2 when a read request given from the processor 1 is received by the memory 2. While a transfer request of the block on the memory 2 is delivered to a secondary cache memory 3 when the read request data is not stored in said block. A transfer request block, if exists, on the memory 3 is transferred to the memory 2 from the memory 3 and stored in the memory 2. At the same time, the processor request data in said block is transferred to the processor 1. Thus the hit factor of the memory 3 is improved.


Inventors:
SENBA KIYOSHI
Application Number:
JP8264885A
Publication Date:
October 28, 1986
Filing Date:
April 19, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Ashida Tan