To enable simple constitution and control and obtain an economical cache memory controller by controlling an area cache control process at intervals of set several minutes according to whether a comparison specified part of an object high-order address is coincident or noncoincedent and a corresponding tag state flag.
An input holding part 110 inputs a request for area cache control which includes at least 1st information 111 indicating the presence of a process request, address information 115, and comparison part specification information 116 and is issued by an instruction processor and holds the respective pieces of information for a necessary process period. Then a control means 120 connects to at least the 1st information 111 which indicates the presence of the area cache control request, a set of state information (ViWi) read out of an adder array according to an intermediate-order address 113, a set (AHITi) of decision results of comparison decision parts 117-119, and the interface signal of a bus interface unit 108, and controls the execution of an area cache control area according to the respective pieces of information.
YAMADA SHINKO
NORO TORU
ISHII TOMOKI
