To improve the effect of a cache memory by storing the command and the data needing high-speed access in the cache memory in advance, and controlling the replacement operation in the cache memory by CPU access thereafter.

This cache memory controller comprises the cache memory 15 for storing the command or the data, an address range designating means 13 for designating an address range storing the command and the like having a priority, a look-ahead controlling means 12 for reading out the command and the like in the address range, a discrimination information storing means for storing the identification information 153 indicating that the command and the like having a priority is stored in a cache line, an adjusting means 14 for adjusting the access request of the look-ahead controlling means 12 and the CPU 11, and a replacement controlling means for determining whether the command and the like stored in the cache line in advance is the command and the like having a priority or not on the basis of the discrimination information 153, and controlling the replacement of the command and the like of the cache line.