To obtain a cache memory that is specialized in respective properties by switching between a processing method for operating a data cache and that of operating as an instruction cache.

This memory includes a code segment register 150 which stores the segment address of a code segment being an instruction storage region and a comparator 160 which compares an address stored in the register 150 with an address stored in an address register 120, makes the line ineffective if read to an instruction is for the last word of the line and also prefetches the next line by deciding whether an access to a cache memory is for an instruction or for data.