To utilize the effect of the grouping of instructions by a compiler and to improve the transferring efficiency of instruction data at the time of success of a branching instruction by synchronizing cache control and an instructing processing speed with each other in a cache memory device installed at an instruction processor (CPU).

The device is provided with a first cache 12 capable of transferring instruction information to CPU 10 and a second cache 12 capable of transferring instruction information to the first cache 12, and the second cache 14 is provided with a means for synchronizing instruction information including plural instructions, which is natural-number-fold with respect to the line length of the first cache 12 and can simultaneously be executed by CPU 10, with a fast clock to transfer to the first cache 12. In addition, the first cache 12 is provided with a means transferring plural instructions, which is transferred from the second cache 14 and can simultaneously be executed by CPU 10, to CPU 10.