Title:
CACHE MEMORY AND ITS FAULT DETECTION METHOD
Document Type and Number:
Japanese Patent JP3494072
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To surely detect an error in a cache memory due to a miss on logical design or a data change.
SOLUTION: A cache memory 100 having an auxiliary address array 120 for storing a copy of a part of an address array 110 and an auxiliary data memory 140 for storing a copy of a part of a data memory 130 detects the non-coincidence of contents between both the memories 130, 140 by a comparator 172. A mode storing circuit 171 stores a storage mode indicating whether write based on a storing instruction is to be reflected to the memory 140 or not and a dynamic mode indicating whether a fill due to a cache miss is to be reflected to the array 120 or not.
Inventors:
Shuzo Wadasaki
Application Number:
JP11755099A
Publication Date:
February 03, 2004
Filing Date:
April 26, 1999
Export Citation:
Assignee:
NEC
International Classes:
G06F12/08; G06F11/28; G06F12/16; (IPC1-7): G06F12/08; G06F11/28; G06F12/16
Domestic Patent References:
| JP3122739A | ||||
| JP6482238A | ||||
| JP3129440A | ||||
| JP5289904A | ||||
| JP535590A |
Attorney, Agent or Firm:
Masahiko Desk (2 outside)
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