PURPOSE: To attain the effective availability of the full capacity of a cache memory by selecting bits after comparing a real address given from an associative memory with that given from a cache directory.

CONSTITUTION: When a cache memory 4 and a cache directory 3 receive access at a real address part in a logical address, the least significant bit of a main address received from an associative memory 2 is invalidated or validated through an AND gate 5 according to a prescribed page size or a half page size. The real addresses read out of the memory 4 and the directory 3 are compared with each other by a comparator 21. When no coincidence is obtained between both real addresses, a FF 10 inverts its holding value to obtain the most significant value bit that gives access to the memory 4 and the directory 3. While the held value is used to access again in the case of a half page size.