Title:
Capacitance measurement
Document Type and Number:
Japanese Patent JP6112494
Kind Code:
B2
Abstract:
A capacitance measurement circuit comprises a differential amplifier with first and second inputs and an output, first and second feedback capacitances, and a reset mechanism. The first input is coupled to a modulated reference voltage and the second input is coupled with a sensor electrode. A first feedback capacitance is coupled between the output and the second input. A second feedback capacitance is coupled between the output and the second input. The reset mechanism resets the first feedback capacitance to a first level of charge and the second feedback capacitance to a second level of charge. During an absolute capacitance measurement phase, the differential amplifier charges the sensor electrode while balancing voltages on the first and second inputs to a voltage level associated with the modulated reference voltage and integrates charge on the sensor electrode to measure capacitance corresponding to a coupling between the sensor electrode and an input object.
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Inventors:
Sharokuhi, Farzanay
Schwarz, Adam
Chapania, Sharoots
Reynolds, Joseph Curse
Datarow, Tracy Scott
Schwarz, Adam
Chapania, Sharoots
Reynolds, Joseph Curse
Datarow, Tracy Scott
Application Number:
JP2015523147A
Publication Date:
April 12, 2017
Filing Date:
July 12, 2013
Export Citation:
Assignee:
Synaptics Incorporated
International Classes:
H03K17/955; G01R27/26; G06F3/041; G06F3/044; H03K17/96
Domestic Patent References:
| JP2008026249A | ||||
| JP2010108501A | ||||
| JP2013541272A |
Foreign References:
| US20060273804 |
Attorney, Agent or Firm:
Ikeda adult
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi