PURPOSE: To enable a capacitor to be enhanced in capacitance by a method wherein one of a pair of opposed electrodes confronts the other electrode through the intermediary of a dielectric in an upper wiring layer, a lower wiring layer, and between the upper and the lower wiring layer.

CONSTITUTION: A lower wiring layer 20 and an upper wiring layer 21 are formed on a board 10 through the intermediary of an interlayer insulating film 11. In the lower wiring layer 20 and the upper wiring layer 21, the electrodes A and B are so arrange as to enable their comb-toothed parts to be engaged with each other. Furthermore, in the upper wiring layer 21, the comb-toothed parts of the electrodes are arranged in AB, AB order, and in the lower wiring layer 20, the comb-toothed parts of the electrodes are arranged in BA, BA order. Therefore, the electrode A of the lower wiring layer 20 confronts the electrode B of the lower wiring layer 21, and the electrode B of the lower wiring layer 21 confronts the electrode A of the lower wiring layer 20. Charge is stored in these three planes, so that a capacitor of this design can be enhanced in electrode area.