Title:
【発明の名称】半導体記憶回路
Document Type and Number:
Japanese Patent JP3151839
Kind Code:
B2
Abstract:
PURPOSE:To make stable a substrate potential and to improve the yield without oscillating a sense amplifying circuit since the power is not supplied to the sense amplifying circuit even when a memory cells to form a pair are both on. CONSTITUTION:Reference current generating circuits 3a and 3b to generate the reference current smaller than the current when memory cells MC1 and MC2 to form a pair are on are provided. Discriminating circuits 4a and 4b to compare the output current of the memory cells MC1 and MC2 with the reference current and decide whether or not the memory cells MC1 and MC2 are on are provided. By the deciding result of the discriminating circuits 4a and 4b, when the memory cells MC1 and MC2 are both on, a power supplying control circuit 5 to stop the supply of the power to a sense amplifying circuit 2 is provided.
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Inventors:
Toshiya Sato
Application Number:
JP3822591A
Publication Date:
April 03, 2001
Filing Date:
March 05, 1991
Export Citation:
Assignee:
NEC
International Classes:
G11C17/00; G11C16/06; G11C29/00; G11C29/04; (IPC1-7): G11C16/06; G11C29/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)