Title:
CARRY LOOK-AHEAD CIRCUIT
Document Type and Number:
Japanese Patent JP3445533
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress an increase in computing time even if the number of bits increases by generating group proper gate signals, group generate signals, and group kill signals in units of a group consisting of multiple bits.
SOLUTION: A CLA circuit is equipped with an AND circuit AN1, a priority encoder PE, and a selector SEL1 by groups of 4 bits and generates proper gate signals PG, generate signals GG, and kill signals KB by groups. The AND circuit AN1 is supplied with all P(3:0) signals and performs AND operation and outputs the result as PG and/or the inverted PGB signal of PG. Multiplexers MUX1 and MUX2 of the selector SE1 input a selector signal S(3:0), selects signals G(3:0) and K(3:0) of bits '1', and outputs them as signals GG and KG of a group.
Inventors:
Makoto Hayakawa
Application Number:
JP18695699A
Publication Date:
September 08, 2003
Filing Date:
June 30, 1999
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F7/00; (IPC1-7): G06F7/00
Domestic Patent References:
| JP1281529A | ||||
| JP264729A | ||||
| JP773019A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)