PURPOSE: To minimize the rise in an average speed and a peak speed of a VC by excluding an idle cell period within a real cell arrival interval among cell streams being components of a path reached to a delay circuit at a prescribed ratio and discharging them.

CONSTITUTION: An FIFO 80 has a write address generating circuit 81, a memory 82 and as read address generating circuit 83 and stores only a real cell in response to a cell write control signal 91, an input cell 92, a cell read control signal 93, and a clock 95 and outputs an output cell 94 and an empty signal 96. A control means 10 eliminates an idle cell block within a real cell arrival interval among cell streams comprising a real cell and idle cells among cell streams comprising real cells and idle cells reached to the FIFO 80 at a prescribed ratio through the on/off control in response to the state of the real cell and remaining idle cells to suppress properly the increase in the cell stream. That is, since the time compression of the cell stream is relaxed, the rise in the average speed and the peak speed is decreased.