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Patent Searching and Data


Title:
CERAMIC MULTILAYER CIRCUIT SUBSTRATE AND ITS MANUFACTURING METHOD AS WELL AS ELECTRONIC DEVICE PACKAGE BODY
Document Type and Number:
Japanese Patent JPH10150269
Kind Code:
A
Abstract:

To lower the electric resistance for lessening the dispersion in the electric resistance and characteristic impedance values to be stabilized while increasing the wiring density by increasing the sectional area of a conductor wiring pattern to exceed a specific ratio of the product of maximum width and film thickness.

Before performing the lamination and bonding steps, a fine conductor paste printed by improved screen printing process in the fine width of 25-50μm and at fine pitch of 150-250μm to is to be set. Through these procedures, the shape deformation in the lamination and bonding steps can be avoided so that a glass ceramic multilayer circuit substrate 15a in fine width also at fine pitch of 150-250μm further having a low resistant conductor wiring in the electric resistance not exceeding 10Ω may be manufactured. In such a constitution, the sectional area of the conductor wiring pattern of the circuit substrate 15a exceed 80% of the product of the maximum width and film thickness of the wiring, thereby enabling the dispersion in the electric resistance etc. to be lessened, and the high density conductor wiring to be realized.


Inventors:
OKAMOTO MASAHIDE
ISHIHARA SHOSAKU
SHOJI FUSAJI
KINOSHITA MADOKA
Application Number:
JP30982696A
Publication Date:
June 02, 1998
Filing Date:
November 21, 1996
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H05K3/46; H01L21/60; (IPC1-7): H05K3/46; H01L21/60
Attorney, Agent or Firm:
Akio Takahashi (1 person outside)