Title:
セラミック基板の製造方法、および、セラミック基板
Document Type and Number:
Japanese Patent JP4938018
Kind Code:
B2
Abstract:
The present invention provides a method for manufacturing ceramic substrate having via hole (s) and a surface wiring pattern electrically connected to the via hole(s), the method comprising the steps of: preparing a sintered ceramic substrate having via hole (s) ; forming over the sintered ceramic substrate a sintered ceramic layer having hole(s) or opening(s) whose bottom is configured to be at least a part of exposed end surface of the via hole(s) by post-firing method; forming inside the hole(s) or opening(s) a conductive portion which electrically connects the surface of the sintered ceramic layer and the via hole(s); and forming over the surface of the sintered ceramic layer a surface wiring pattern electrically connected to the conductive portion. According to the above method, even when the sintered ceramic substrate is manufactured by co-firing method, it is possible to highly accurately control the connecting position of the via hole(s) and the surface wiring pattern, but also possible to inhibit problems like short circuit. Thus, it is capable of forming a highly-accurate and fine wiring pattern on the ceramic substrate.
Inventors:
Yasuyuki Yamamoto
Sugawara Lab
Masakatsu Maeda
Sugawara Lab
Masakatsu Maeda
Application Number:
JP2008533187A
Publication Date:
May 23, 2012
Filing Date:
September 05, 2007
Export Citation:
Assignee:
Tokuyama Corporation
International Classes:
H05K1/11; H01L23/12; H05K1/03; H05K3/24; H05K3/40; H05K3/46
Domestic Patent References:
| JP2001156413A | ||||
| JP2000323619A | ||||
| JP9275166A | ||||
| JP6144935A | ||||
| JP5283272A | ||||
| JP201062522A |
Attorney, Agent or Firm:
Noriyuki Yamamoto
Akihiko Yamashita
Kishimoto Tatsuto
Akihiko Yamashita
Kishimoto Tatsuto