PURPOSE: To detect an error of a data which is outputted from a gate or a register, in a controller, by providing a parity checking circuit on a load information register.

CONSTITUTION: A data DATA which has been recorded in a memory 2 is outputted to a gate 3 and a parity checking circuit 4 from the memory 2. The circuit 4 executes a parity check of DATA, and in case when there is no error, DATA is inputted to the gate 3 as it is. DATA which has been inputted to the gate 3 is outputted to a load information register 5 of a channel controller 1, and the register 5 outputs the DATA which has been inputted, to an object channel 7. In this case, a parity checking circuit 6 checks a parity of the DATA which has been outputted from the register 5, over again, and detects whether an error has been generated in the DATA between the gate 3 and the register 5. In case when there is no error, the DATA is outputted to each channel 7.