PURPOSE: To reduce the buffer memory capacity, by writing information only at the H period where a character signal is superimposed into a buffer memory.

CONSTITUTION: A signal 25 detecting at which H period the character signal is multiplexed is outputted from an FF circuit 24. A synchronizing signal in the unit of byte obtained from a framing code signal is used as a set signal of the FF circuit 24 and a signal 26 detecting the 34-byte count from an address signal of an address generating circuit 8 of a buffer memory 4 is used as a reset signal. The latch is attained only at the superimposed period of the character signal, by using this detecting signal and ANDing it with a sampling clock being the clock of a byte counter section 5 at an AND circuit 18. Further, the address is not generated for the character signal only at the superimposed period as to the address generating section 8 and no write signal 17 is generated.