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Patent Searching and Data


Title:
CHARGED-PARTICLE-BEAM TESTING APPARATUS AND SEMICONDUCTOR-INTEGRATED-CIRCUIT TESTING APPARATUS
Document Type and Number:
Japanese Patent JPH07151836
Kind Code:
A
Abstract:

PURPOSE: To obtain an LSI image in which an abnormal portion can be detected easily.

CONSTITUTION: A trigger signal is generated at the beginning of every test pattern, it is delayed by a set delay amount by a delay means 23, electron-beam pulses are directed to an IC 15 by its delayed output, and their secondary electrons are detected by a detector 16 and taken in by one out of memories 18, 19 as image data. It is repeated at every horizontal scanning operation to increase a delay amount by a definite amount at every trigger. When data of one frame is acquired, an acquisition completion signal is sent to a signal generator 11. Whenever the signal generator 11 receives the acquisition completion signal, it alternately changes an operating condition such as a power-supply voltage, and it makes the same test. In addition, a condition signal is generated, and the storage of the image data is changed over alternately between the memories 18, 19, and the difference in the data between the memories 18, 19 is displayed.


Inventors:
KAWAMOTO HIROMOTO
KURIHARA MASAYUKI
IWAI TOSHIMICHI
GOSEKI AKIRA
Application Number:
JP30161893A
Publication Date:
June 16, 1995
Filing Date:
December 01, 1993
Export Citation:
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Assignee:
ADVANTEST CORP
International Classes:
G01R31/302; H01L21/66; G01N23/225; (IPC1-7): G01R31/302; G01N23/225; H01L21/66
Attorney, Agent or Firm:
Kusano Taku (1 person outside)