PURPOSE: To obtain a stable and accurate PLL phase locked loop circuit by detecting that two input terminals are both turned high and interrupting two outputs by which the output signal of a charging pump circuit is outputted at this time.

CONSTITUTION: In signals from an input up terminal 34 and an input down terminal 36 from a digital phase comparater 40, both signals from the terminals 34, 36 are turned high is detected with two NPN transistors 10, 11 carrying out a switching operation the NPN transistor 13 levelshifting the outputs and resistor 14, 18. Then, a transistor 28 switching a transistor 26 which controls an output transistor 30 for absorbing by the output and an output transistor 31 for discharging by the output are controlled. The two transistors 21 and 22 constituting OR with the signal of the input up terminal are provided. Thus, the offsetting of the charging pump circuit 50 is eliminated and the stable and accurate PLL circuit is obtd.