PURPOSE: To realize the chattering elimination circuit able to avoid production of glitch noise regardless of a timing when a state value of an input signal is inverted in the case plural chattering elimination circuits are employed for a digital circuit.

CONSTITUTION: First and 2nd chattering elimination sections 1,2 transfer respectively an input signal IN1 synchronously with sampling signals C1, C2 to eliminate chattering included in the input signal. Then an AND gate 3 (or OR gate) outputting AND gate 3 (or OR gate) of the outputs of the 1st and 2nd chattering elimination sections 1,2 is provided and the output of the AND gate 3 (or OR gate) is outputted as an output signal OUT1. Moreover, the sampling signals C1, C2 are signals whose frequencies differ from each other.