PURPOSE: To decrease the number of input and output terminals and to attain a large-scale integration for a check code generating and error correcting IC, by using the input terminals of the 1st and 2nd receivers and the output terminals of the 1st and 2nd drivers as the 1st and 2nd common terminals.
CONSTITUTION: An IC is provided with the 1st and 2nd receivers 10 and 12, the 1st and 2nd drivers 11 and 13, a check code generating circuit 14, a syndrome generating circuit 15, a decoding circuit 16, a correcting circuit 17, selecting circuits 18 and 19, a writing register, a reading register, etc. The input terminal of the receiver 10 and the output terminal of a driver 11 are connected to a system bus S as common terminals; and at the same time the input terminal of the receiver 12 and the output terminal of the driver 13 are connected to a memory bus M as common terminals. Thus the number of input and output terminals is decreased for a check code generating and error correcting IC, and a large-scale integration is facilitated with said IC.
OONO KUNIO
SHIYOUDA HIROAKI
| JPS5528130A | 1980-02-28 |