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Title:
CHECK METHOD FOR BUS SIGNAL LINE
Document Type and Number:
Japanese Patent JPS5755435
Kind Code:
A
Abstract:

PURPOSE: To easily detect a failure of signal line, by connecting a controller and a plurality of driver circuits with a common bus signal line and a driver circuit selecting signal line, and providing a comparator together with a receiver circuit to the controller.

CONSTITUTION: A controller CNT and a plurality of driver circuits DRAWDRX are connected with common signal buses L1, L2 and a driver selecting signal line SEL. Load resistors R1, R3 and R2, R4 are connected to the signal buses L1, L2. When the driver circuit DRA is selected, a switch SWA turns on to be active, and an output appears at terminals 3A, 4A, and current iA, iB flow to the signal lines L1, L2. When a comparison voltage Vx of comparators COM1, COM2 is set to iR/2 by taking R1=...R4=R, and iA=iB=i, if the voltage is normal, the outputs of the comparators are 0, but if the potential on the signal lines L1, L2 is changed because of any reason, since the comparators cause outputs to detect failures through the combination with the selecting state of a selecting signal SEL. Thus, the failure in signal lines is discovered with a simple device.


Inventors:
HAMURA YOSHIHIRO
Application Number:
JP12990380A
Publication Date:
April 02, 1982
Filing Date:
September 17, 1980
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F3/00; G06F11/00; G06F13/00; G06F13/36; (IPC1-7): G06F3/00; H04L11/00
Domestic Patent References:
JPS5378730A1978-07-12
JPS5051638A1975-05-08
JPS5328346A1978-03-16