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Title:
CHIP SIZE PACKAGE TYPE PACKAGE FOR SEMICONDUCTOR AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2004079716
Kind Code:
A
Abstract:

To provide a CSP (chip size package) type package having a wide external terminal pitch and to provide its manufacturing method.

A first resin coat layer for insulating electrically an LSI (large scale integrated circuit) pad 2 and a first contact electrode 4 which are formed on an individualized LSI chip 1 is extended to the outside of the outer rim end of the LSI chip 1 to enlarge a package so as to be bigger than the LSI chip 1. An intermediate wiring layer 5 and a part of a second contact electrode 7 are formed on the first resin coat layer 3 formed at the outside of the outer rim end of the LSI chip 1 while a CSP (chip size package) pad 8 and a CSP bump 9 are formed on the second contact electrode 7. The CSP pad 8 and the CSP bump 9 are formed at the outside of the outer rim end of the LSI chip 1. Accordingly, the pitch of these external terminals can be wider that that of the LSI pads 2 arranged so as to be neighbored with a narrow pitch whereby the design and the manufacture of an outer substrate are facilitated.


Inventors:
HORIE MASANAO
Application Number:
JP2002236640A
Publication Date:
March 11, 2004
Filing Date:
August 14, 2002
Export Citation:
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Assignee:
NEC ELECTRONICS CORP
International Classes:
H01L21/60; H01L23/12; H01L23/31; H01L23/485; (IPC1-7): H01L23/12
Attorney, Agent or Firm:
Masanori Fujimaki