To obtain an on-chip voltage multiplying circuit by making up a network which comprises N stages arranged in series each having a switch having upper and lower terminals and also having a capacitor connected to the upper terminal.

A plurality of capacitors Ci (i=1,...n) arranged in series are broken by a set of switches Tj (j=2,...n), terminal and intermediate nodes of which are connected to a supply voltage Vdd through sets of switches T1 and Di (i=1,...N) and further grounded through a set of switches Si (i=1,...N). An output current is extracted from the last capacitor CN and further from another switch T (N+1). An NMOS transistor NC-T (N+1) inserted between the upper terminal of the capacitor CN and an output of the final stage realizes an output transistor T (N+1).