Title:
CHROMA SIGNAL REPRODUCTION CIRCUIT
Document Type and Number:
Japanese Patent JP3523890
Kind Code:
B2
Abstract:
PURPOSE: To use plural chroma signal processing methods in parallel with a small circuit scale.
CONSTITUTION: An address counter 5, a memory 2, an arithmetic section 6 and a voltage controlled oscillator 13 or the like are used to form an APC loop, burst data are written in the memory 2 based on a reference clock synchronously with a burst signal and feedback control is made so that the burst data of a specific address written in the memory 2 are specific phase data in the lock state of the APC loop and the data representing a lead degree of a phase are calculated based on the phase data of the memory 2 by microprogramming processing, an ACC loop is formed by a multiplier 1, the memory 2, the arithmetic operation section 6, a ROM 15 or the like and it is utilized to write specific phase data to the specific address of the memory 2 to calculate the difference data of the amplitude level by the microprogramming processing and feedback control is attained by making the amplitude level of the burst signal inputted to the memory 2 constant through the use of the difference data.
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Inventors:
Miyazaki, Shinichiro
Watanabe, Kazuo
Watanabe, Kazuo
Application Number:
JP16343293A
Publication Date:
April 26, 2004
Filing Date:
July 01, 1993
Export Citation:
Assignee:
SONY CORP
International Classes:
H04N9/45; H04N9/455; H04N9/68; (IPC1-7): H04N9/45
Attorney, Agent or Firm:
橋本 剛