PURPOSE: To provide the ciphered data processor, for which resistance to deciphering is improved, by directly integrating the value of an address into a conversion formula as the key inputs of ciphering conversion and deciphering conversion.
CONSTITUTION: Corresponding to an address output 303 of a CPU 300, ciphered data outputted to a data output 201 of an external memory 200 are inputted to a cipher input 401 of a deciphering circuit 400, and the deciphered result with a key input 403 as a key is outputted from a decipher output 402 and applied to a data input 301 of the CPU 300. In this case, since a data output 302 of the CPU 300 is written out to the external memory 200 without being deciphered, when reading the written-out data again by the CPU 300, it is necessary not to perform the conversion by judging this by the deciphering circuit 400. Thus, since the information ciphered on the memory 200 can not be used without providing this device and secret information, a program or data can be prevented from being stolen by copying the memory 200.
OGURA NAOSHI
JPS59173847A | 1984-10-02 | |||
JPS5987546A | 1984-05-21 |