CIPHERING AND DECIPHERING DEVICE

Japanese Patent JP3295887

B2

PROBLEM TO BE SOLVED: To accelerate the processing speed by processing data at the high-order part of a register and decreasing the number of instructions when the register length is long.
SOLUTION: For example, three 32-bit data α0, α1, and β are received; and their high-order 8-bit parts are denoted as a0, a1, and b0 and the low-order 8-bit parts are denoted as a3, a2, and b1. An XOR process part 110 exclusively ORs those data, bit by bit, and stores the results in a register T1. Here, outputs (a1)1 and (a2)1 of parts which vary in value are arranged in the high-order and low-order 8-bit parts of the register T1. Therefore, two processes can be performed by one operation. Then an S box process part 110 operates S((a1)1, (a2)1, and 1). Consequently, the low-order 8 bits of the register T1 are arranged at the high-order 8 bits of a register T2, T3=T1+T2+224 is calculated, and the result is stored in a register T3. At this time, digit overflows are all ignored. Similar calculates are repeated.

Hiroki Ueda
Masayuki Abe
Atsushi Fujioka

JP28503096A

June 24, 2002

October 28, 1996

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Nippon Telegraph and Telephone Corporation

G09C1/00; (IPC1-7): G09C1/00

JP62113191A

Ａ ｈｉｇｈ ｓｐｅｅｄ ｓｏｆｔｗａｒｅ ｉｍｐｌｅｍｅｎｔａｔｉｏｎ ｏｆ ｔｈｅ Ｄａｔａ Ｅｎｃｒｙｐｔｉｏｎ Ｓｔａｎｄａｒｄ，Ｃｏｍｐｕｔｅｒ Ｓｅｃｕｒｉｔｙ，１９９５年１０月 ２日，Ｖｏｌ．１４，Ｎｏ．４，ｐ．３４９−３５７
Ａ ｈｉｇｈ−ｐｅｒｆｏｒｍａｎｃｅ ｓｏｆｔｗａｒｅ ｉｍｐｌｅｍｅｎｔａｔｉｏｎ ｏｆ ｔｈｅ Ｄａｔａ Ｅｎｃｒｙｐｔｉｏｎ Ａｌｇｏｒｉｔｈｍ，Ｊｏｕｒｎａｌ ｏｆ Ｍｉｃｒｏｃｏｍｐｕｔｅｒ Ａｐｐｌｉｃａｔｉｏｎｓ，１９９１年１１月２９日，Ｖｏｌ．１４，Ｎｏ．４，ｐ．３４３−３６２
Ａｎ ａｐｐｌｉｃａｔｉｏｎ ｏｆ ａ ｆａｓｔ ｄａｔａ ｅｎｃｒｙｐｔｉｏｎ ｓｔａｎｄａｒｄ ｉｍｐｌｅｍｅｎｔａｔｉｏｎ，Ｃｏｍｐｕｔｅｒ Ｓｙｓｔｅｍｓ，１９９０年 ３月１９日，Ｖｏｌ．１，ＮＯ．３，ｐ．２２１−２５４

Suguru Kusano

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