To prevent erroneous detection even if a signal where a specified cycle pattern is parallel expanded is inputted.

Parallel signal lines are monitored by change point detecting circuits 210-213, input disconnection is detected so as to adopt the output to be active unless an input signal changes to be high or low for a fixed period and a state is adopted as the sleep one after a fixed time elapses when a change point appears in an active state. It is judged whether signal input disconnection or not from the pieces of change point detecting information by a pattern identifying circuit 22. The logical level of the respective signal lines is discriminated at the time of detecting input disconnection concerning the whole signal lines. Signal input disconnection is judged and the output is made to be active at the time of only a specified pattern of data. Thus, the outputs of the change point detecting circuits 210-213 of the respective lines and logical level information of the respective signal lines are coupled so that a transmission pattern at the time of serial transmission is presumed and disconnection is judged.