Title:
CIRCUIT DEVICE BY COMPLEMENTARY MOS TECHNIQUE
Document Type and Number:
Japanese Patent JPH02117208
Kind Code:
A
Abstract:
PURPOSE: To minimize current consumption by symmetrically constituting the geometry of input transistors(TRs) and asymmetrically constituting that of load TRs. CONSTITUTION: Prescribed offset voltage is generated by designing or dimensioning the geometric ratio of TRs in a circuit device. Input TRs M1, M2 are symmetrically constituted and load TRs M3, M4 are asymmetrically constituted. The geometry of TRs to be output driver circuits M6, M9 matches the operational characteristic of a differential comparator. These processing can be attained by correspondingly dimensioning the geometric ratios of channel width to channel length of these TRs. The geometric ratio of the TRs M1, M2 is equal to '1' and the geometric ratio of channel width to channel length of the load TR M4 is set up to a value (a)>1 based on the TR M3.
Inventors:
HAINTSU CHITSUTA
Application Number:
JP24325289A
Publication Date:
May 01, 1990
Filing Date:
September 18, 1989
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H01L27/04; H03F3/45; H03K5/08; H01L21/822; H03K5/24; (IPC1-7): H01L27/04; H03F3/45; H03K5/08
Attorney, Agent or Firm:
Tomimura Kiyoshi