Title:
CIRCUIT FAULT SIMULATOR
Document Type and Number:
Japanese Patent JPS57138242
Kind Code:
A
Abstract:
PURPOSE: To reproduce various fault causes by supplying an optional bit pattern to an MODEM.
CONSTITUTION: Even if malfunction occurs because a bit pattern[010,0001]= (61)16 is tranmitted to a center although a bit pattern[0110,0010]=(62)16 equivalent to an F is sent to an MODEM for, e.g., a failure in connection cord contact between a terminal equipment and the MODEM, a code which corresponds to the bit pattern[0110,0001]is undefined and the terminal equipment can not generate it, so that it can not be reproduced. For this purpose, a simulator capable of generating an optional hexadecimal number is connected to the MODEM to reproduce the undefined bit pattern optionally.
Inventors:
KITAYAMA HIROSHI
Application Number:
JP2378481A
Publication Date:
August 26, 1982
Filing Date:
February 20, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04L69/40; G06F13/00; H04B3/46; H04B17/00; H04L1/24; (IPC1-7): G06F3/04; H04B17/00; H04L13/00