To obtain a DMA(direct memory access) control circuit with high efficiency for improving the performance of a system as a whole in which a high-speed CPU or a memory and a low-speed memory or an I/O device or the like coexist.

This circuit is provided with a random dynamic random access memory(RDRAM) 11 which is a high-speed main storage memory, exclusive RDRAM I/F 12, CPU 1 for a high-speed system, high speed system bus 2, low speed memory 10, low-speed system bus 8, high-speed side bus control part 5 for controlling the high speed system bus 2, and low-speed side bus control part 6 for controlling a low-speed system bus 8. Thus, the CPU 1 and a RDRAM 11 can be independently operated. Therefore, it is not necessary for a CPU to continue to wait until DMA transfer is ended, even if a general memory is adopted which is not equipped with any special switching controlling function, and a DMA transferring time can be shortened. Also, high convenience, high speeding, and high efficiency can be easily obtained.