Title:
CIRCUIT AND METHOD FOR SELECTING SIGNAL
Document Type and Number:
Japanese Patent JP3199053
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a multi-stage multiplexer type signal selecting circuit with which power consumption is saved by suppressing a switching operation.
SOLUTION: The circuit is constituted of seven multiplexers M00-M20 which are connected in a three-stage tree shape. They select one of input signals A and B in accordance with control signals S2, S1 and S0 and output it when an updating permission signal ENA of a state 1 is inputted from an external part, supply the updating permission signal E of the state 1 to the low-order multiplexer which is selected and supply the updating permission signal E of the state 0 to the low-order multiplexer which is not selected. The multiplexer to which the signal E of the state 0 is supplied holds previous contents and the switching operation is stopped. In a result, switching is operated only in the multiplexer where the input signals D0-D7 outputted as an output signal OUT pass through and one of the input signals D0-D7 is selected and outputted to an external bus.
Inventors:
Takahiko Nishizawa
Application Number:
JP4291999A
Publication Date:
August 13, 2001
Filing Date:
February 22, 1999
Export Citation:
Assignee:
NEC
International Classes:
H03K5/00; H03K17/00; H03K17/693; H04Q3/52; (IPC1-7): H03K17/00; H03K5/00; H03K17/693; H04Q3/52
Domestic Patent References:
| JP9312558A | ||||
| JP677792A | ||||
| JP6165623A | ||||
| JP62105524A | ||||
| JP61173516A | ||||
| JP1293796A | ||||
| JP60201795A |
Attorney, Agent or Firm:
Furuzo Satoshi (1 person outside)