Title:
回路パターン検査装置、および回路パターン検査方法
Document Type and Number:
Japanese Patent JP4006119
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To quickly set an inspection region with satisfactory hondleability by providing an inspection region setting means on a displayed wafer map and as well as displaying the number of inspection chips, an inspection area, estimated inspection time or the like, together with a wafer map display image. SOLUTION: A region to be inspected is clicked or dragged (chip selected) for specification from among effective chips on a wafer map 101 and a map in chips. Since all the chips in a wafer are defaulted to be a region to be inspected, desired chips or regions can be specified to set an inspection region, while alternately, chips or regions which are not to be inspected can be specified thereby setting a region which is not to be inspected. In this case, the inspection region can also be specified by referring to a scanning electron microscope(SEM) image displayed on a right-hand screen 105. Thereafter, a sampling rate is selected from a combo box of a sampling rate input region 103. The number of chips inspected, the total number of chips, the inspection area, the sampling rate and estimated inspection time are respectively displayed on the lower right of the screen.
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Inventors:
Yasuhiko Nara
Takashi Hiroi
Takashi Hiroi
Application Number:
JP34029398A
Publication Date:
November 14, 2007
Filing Date:
November 30, 1998
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G01B21/30; G01B11/30; H01J37/22; G01B15/00; G01B15/08; G01N21/88; G01N21/93; G01N21/956; G01N23/225; G01R31/302; H01L21/66
Domestic Patent References:
| JP10213422A | ||||
| JP8124977A | ||||
| JP10135288A | ||||
| JP10294345A | ||||
| JP6124678A | ||||
| JP5961779A | ||||
| JP59214151A |
Attorney, Agent or Firm:
Yukihiko Takada