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Title:
CIRCUIT FOR PREVENTING APPLICATION OF ERRONEOUS VOLTAGE
Document Type and Number:
Japanese Patent JPH05176451
Kind Code:
A
Abstract:

PURPOSE: To protect an electronic appliance from being applied with a high voltage even if a high voltage supply cable is connected inadvertently with the low voltage input section of the electronic appliance by detecting the voltage level to be fed to the electronic appliance and then switching a relay for feeding power to the electronic appliance.

CONSTITUTION: When +12V voltage is applied between terminals 1, 2 and the voltage E1 reaches 4.5V at time t1, an NPN transistor(Tr) Q2 is turned ON to feed a current through the coil of a relay RL2 thus closing the contact r12 thereof. When the voltage E1 reaches 5.5V at time t2, TrQ1 turns ON to feed current through the coil at a relay RL1 thus opening the contact r11 thereof. Consequently, the Tr Q2 is turned OFF to interrupt current supply to the coil of the relay RL2 thus opening the contact r12 thereof. Since the contact r11 is closed until time t2, voltage applied between terminals 3, 4 is outputted as it is but the output voltage does not reach a level (about 7V) for breaking down the logic circuit in an electronic appliance. When the contact r11 is opened, the voltage between the terminals 1, 2 is not outputted to the terminals 3, 4.


Inventors:
SAITO SUSUMU
Application Number:
JP35658891A
Publication Date:
July 13, 1993
Filing Date:
December 25, 1991
Export Citation:
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Assignee:
NEC IBARAKI LTD
International Classes:
H02H11/00; H02J1/00; (IPC1-7): H02H11/00; H02J1/00
Attorney, Agent or Firm:
Masaki Yamakawa



 
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