To shorten the time required for determining defective and non-defective semiconductor integrated circuits.

This test circuit is provided with a signature (N vector) 17 when a test pattern is an N vector (N is a natural number), and a signature (M vector) 16 when the test pattern is an M vector (M is a natural number, and M<N). A comparator 15 performs comparison determination on both a compression value of an output signal value, outputted from a core_logic/memory 13 to which the test pattern of the M vector is inputted and held in an MISR (Multiple Input Signature Register) 14, and the signature (N vector) 16. In the case that the result of the comparison determination is non-defective, comparison determination is performed on both a compression value of an output signal value, outputted from the core_logic/memory 13 to which the test pattern of the N vector is successively inputted and held in the MISR 14, and the signature (N vector ) 17.