Title:
AND CIRCUIT AND WORD LINE DRIVING CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3088496
Kind Code:
B2
Abstract:
PURPOSE: To reduce the load capacity of a clock output line, to reduce an area of each AND circuit, and also, to shorten its internal delay time, in a clock synchronization type word line driving circuit provided with 2n pieces of AND circuits using a bipolar CMOS circuit technique.
CONSTITUTION: Each AND circuit 608i (i=1-2n) is constituted of total four pieces of transistors of a P channel MOSFET 201, a first and a second N channel MOSFETs 202, 203 and an NPN bipolar transistor 204. To a source of the P channel MOSFET 201, and a gate of the P channel MOSFET 201 and a gate of a first N channel MOSFET 202, and a gate of a second N channel MOSFET 2O3, and an emitter of the NPN bipolar transistor 204, a forward turn clock output line 603A, a negative logical address output line 606i, an inversion clock output line 603B, and a word line 609i to be selected are connected, respectively.
Inventors:
Tomohiro Kurozumi
Application Number:
JP19443491A
Publication Date:
September 18, 2000
Filing Date:
August 02, 1991
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/413; H01L21/8249; H01L27/06; H03K19/08; H03K19/20; (IPC1-7): H03K19/08; G11C11/413
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)