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Title:
CLAMP CIRCUIT
Document Type and Number:
Japanese Patent JPH05153432
Kind Code:
A
Abstract:

PURPOSE: To clamp an input MUSE base band signal at an accurate level at all times.

CONSTITUTION: A switch circuit 28 gives an input signal to the clamp circuit 12 when a MUSE base band signal in the state of out of synchronism is inputted. A maximum value detection circuit 18 and a minimum value detection circuit 20 detect the maximum value and the minimum value of the input signal and a center value detection circuit 22 detects a center level based on them. A clamp level of the clamp circuit 12 is set equal to the center level to clamp the input signal. When the input signal is in the synchronization state, the input signal is given to a clamp circuit 14, in which the usual clamping is implemented. Thus, a delay in synchronization locking at out of synchronism is avoided.


Inventors:
SASAKI TORU
HOSOYA NOBUKAZU
Application Number:
JP31675391A
Publication Date:
June 18, 1993
Filing Date:
November 29, 1991
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H03K4/02; H03K5/00; H03K5/007; H04N5/18; H04N7/00; H04N7/015; (IPC1-7): H03K4/02; H03K5/00; H04N5/18; H04N7/00
Attorney, Agent or Firm:
Yoshito Yamada



 
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