To provide a clock control type microprocessor system which reduces the power consumption when the microprocessor has a margin of processing capability in a microprocessor system which needs to have its clock frequency set so that an arithmetic processing time is not shorter than a sampling cycle of input.

An arithmetic delay detecting circuit 13 receives an arithmetic completion flag 26 of the microprocessor 11 to detect how much the operation of the microprocessor is delayed, and generates a clock frequency control signal 27 corresponding to the operation delay and a variable frequency clock generating circuit 14 switches the main clock frequency of the microprocessor 11 to a low frequency when the operation delay is small and to a high frequency when large by using the clock frequency control signal 27. Consequently, the processing capability of the microprocessor 11 is optimized to reduce the power consumption.