Title:
クロック補正装置及びクロック補正方法
Document Type and Number:
Japanese Patent JP6783535
Kind Code:
B2
Abstract:
A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.
Inventors:
Shingo Adachi
Application Number:
JP2016060142A
Publication Date:
November 11, 2020
Filing Date:
March 24, 2016
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
H03K5/12; G06F1/10; H03K5/04; H03K5/131
Domestic Patent References:
| JP2007102483A | ||||
| JP2011138342A |
Attorney, Agent or Firm:
Hide Tanaka Tetsu
Hideaki Shioya
Hideaki Shioya