Title:
CLOCK EXTRACTING CIRCUIT
Document Type and Number:
Japanese Patent JPS63249976
Kind Code:
A
Abstract:
PURPOSE:To stably eliminate a need of adjustment by adding a frequency comparator which generates the output in accordance with the frequency difference between the reference signal and a clock. CONSTITUTION:An input digital signal passes a gate 1 and has the phase compared with that of the clock by a phase comparator 2 unless it is not dropped out, and the clock has the frequency compared with that of the reference signal by a frequency comparator 7. Respective outputs are inputted to a loop filter after being added by an adder 3, and the output is inputted as the control voltage to a VCO 5, and the oscillation output has the frequency divided by 1/2 in a frequency divider 6 to generate the clock synchronized with the digital signal. If the digital signal is dropped out, the digital signal is stopped by the gate 1 and the output of the phase comparator 2 disappears, and therefore, the clock frequency is approximately equalized to the reference frequency by the frequency control of the frequency comparator 7. Thus, adjustment is unnecessary and the capture range is stable even in case of the variation of temperature, and slip of the clock for drop-out is reduced.
Inventors:
YASUDA HIROSHI
NAKAMURA MASAYOSHI
HARUI MASANORI
KOBA MASAO
NISHIOKA AKIHIKO
NAKAMURA MASAYOSHI
HARUI MASANORI
KOBA MASAO
NISHIOKA AKIHIKO
Application Number:
JP8501387A
Publication Date:
October 17, 1988
Filing Date:
April 07, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03L7/113; G11B20/14; H03L7/10; H03L7/14; (IPC1-7): G11B20/14; H03L7/10; H03L7/14
Domestic Patent References:
| JPS61288622A | 1986-12-18 | |||
| JPS5967731A | 1984-04-17 |
Attorney, Agent or Firm:
Tomoyuki Takimoto (1 person outside)