Title:
CLOCK GENERATING CIRCUIT AND SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP2018042167
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To suppress generation of fluctuations in delay time of a frequency divided clock caused by temperature fluctuations.SOLUTION: A clock generating circuit 1 includes: a frequency divided part 16 generating a frequency divided clock of a frequency 1/N times (where, N is an integer of two or more) as many as a frequency of a reference clock by frequency-dividing the reference clock; a distributor 13 for distributing the reference clock to a first path provided with an output terminal 17a of the reference clock and a second path provided with the frequency divided part 16. The frequency divided part 16 includes at least one amplifier, at least one frequency dividing circuit, and a correction circuit provided between the amplifier and the frequency dividing circuit and correcting a level of an input clock input into the frequency dividing circuit.SELECTED DRAWING: Figure 3
Inventors:
YODA TOMOYA
TSUCHIYA SHOICHI
KITAYAMA YASUO
TSUCHIYA SHOICHI
KITAYAMA YASUO
Application Number:
JP2016176250A
Publication Date:
March 15, 2018
Filing Date:
September 09, 2016
Export Citation:
Assignee:
NIHON DEMPA KOGYO CO
International Classes:
H03K21/00; H03K5/00; H03K5/13; H03K23/00; H03L7/08; H03L7/183
Attorney, Agent or Firm:
Izumidori
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