CLOCK GENERATION CIRCUIT AND ADJUSTABLERING OSCILLATOR CIRCUIT

Title:

CLOCK GENERATION CIRCUIT AND ADJUSTABLERING OSCILLATOR CIRCUIT

Document Type and Number:

Japanese Patent JPH0879060

Kind Code:

A

Abstract:

PURPOSE: To provide a frequency-adjustable ring oscillator structure. CONSTITUTION: A digital ring oscillator 32 incorporates a circuit loop having at least of one inverted gate 52 and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between the output and input of the inverted gate 52. A multiplexer 88 selects among the series of taps in accordance with a tap selecting signal. A clock monitor circuit 62 is connected and generates a digital clock cycle count by comparing clock outputs with a reference clocking signal. A programmed microcontroller generates a tap selecting signal as the function of the digital clock cycle count and a desired clock output frequency setting point. A synchronous circuit can be synchronized to the logical state of a succeeding adjustable clocking signal outputted from the oscillator 32.

More Like This:

JP5294019	Oscillator
JPS60214627	RESET CIRCUIT
JPH0260223	RETRIGGERABLE MONOSTABLE MULTIVIBRATOR CIRCUIT

Inventors:

JIEEMUZU EI HENSON
SUKOTSUTO II RITSUCHIMONDO
UIRIAMU AARU EIKIN JIYUNIA

Application Number:

JP13957995A

Publication Date:

March 22, 1996

Filing Date:

June 06, 1995

Export Citation:

Click for automatic bibliography generation Help

Assignee:

QUANTUM CORP

International Classes:

H03K3/02; G06F1/08; H03K3/03; H03K3/78; H03L7/06; H04L7/00; H04L7/033; (IPC1-7): H03L7/06; H03K3/02; H03K3/78

Attorney, Agent or Firm:

深見久郎（外３名）

Next Patent: PHASE LOCK LOOP CIRCUIT AND PULSE SUPPLY/GENERATION