Title:
クロック生成回路、スイッチング電源装置及び半導体装置
Document Type and Number:
Japanese Patent JP7231991
Kind Code:
B2
Abstract:
A clock generation circuit, which generates an output clock using an external clock as a target clock, includes a circuit arranged to change the output clock to high level in synchronization with an up edge of the target clock, circuits arranged to generate first and second ramp voltages with a period of interval between neighboring up edges of the target clock, and a circuit arranged to hold a comparison voltage corresponding to a second ramp voltage when an up edge of the target clock occurs. The level of the output clock is changed from high level to low level based on a comparison result between the first ramp voltage and the comparison voltage.
Inventors:
Menghiro Yoshida
Fukushima Shun
Fukushima Shun
Application Number:
JP2018114197A
Publication Date:
March 02, 2023
Filing Date:
June 15, 2018
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H03K5/04; G06F1/08; H02M3/155
Domestic Patent References:
| JP2009164875A | ||||
| JP201738150A | ||||
| JP8107312A | ||||
| JP2016134916A | ||||
| JP2006287736A | ||||
| JP3283912A |
Attorney, Agent or Firm:
Patent Attorney Corporation Sano Patent Office
Previous Patent: Auxiliary sound collection member, sound processing system, and sound processing method
Next Patent: FULL-ROTATING BOBBIN CASE
Next Patent: FULL-ROTATING BOBBIN CASE