Title:
集積回路用のクロック・ジェネレータ
Document Type and Number:
Japanese Patent JP4034781
Kind Code:
B2
Abstract:
A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.
Inventors:
Barnes, Jeffrey, Elle
Drek, alan, jay
Gothal, Uttam, Chamarind
Noka, Kevin, Jay
Drek, alan, jay
Gothal, Uttam, Chamarind
Noka, Kevin, Jay
Application Number:
JP2004530065A
Publication Date:
January 16, 2008
Filing Date:
July 10, 2003
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H03K3/353; H03B5/12; H03K5/15; H03K3/354
Other References:
J.Craninckx他,「A 1.8GHz Low-Phase-Noise Spiral-LC CMOS VCO」,IEEE 1996 Symposium on VLSI Circuits Digest of Technical Paper,米国,IEEE,1996年,pp30-31,LC CMOS VCO
A.Rofougaran他,「A 900MHz CMOS LC-Oscillator with Quadrature Outputs」,1996 IEEE International Solid-State Circuits Conference,米国,IEEE,1996年,Session 24 Analog Techniques,pp392-393
B.Razavi,「A 1.8GHz CMOS Voltage-Controlled Oscillator」,1997 IEEE International Solid-State Circuits Conference,米国,IEEE,1997年,Session 23 Analog Techniques,pp388-389,LC CMOS VCO
A.Rofougaran他,「A 900MHz CMOS LC-Oscillator with Quadrature Outputs」,1996 IEEE International Solid-State Circuits Conference,米国,IEEE,1996年,Session 24 Analog Techniques,pp392-393
B.Razavi,「A 1.8GHz CMOS Voltage-Controlled Oscillator」,1997 IEEE International Solid-State Circuits Conference,米国,IEEE,1997年,Session 23 Analog Techniques,pp388-389,LC CMOS VCO
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno