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Patent Searching and Data


Title:
CLOCK MODE SETTING ERROR DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPS62226739
Kind Code:
A
Abstract:

PURPOSE: To easily and quickly detect error by providing a phase comparison section and a phase change quantity supervisory section in a communication equipment, and using the communication equipment to detect a clock mode setting error.

CONSTITUTION: The communication equipment 1 consists of an oscillator 10, a phase comparison section 11 and a phase change supervisory section 12. The oscillator 10 sends a clock ST to the phase comparator 11 and the terminal equipment. The phase comparison section 11 consists of differentiation circuits 111,112 and the comparator 113, and the phase of the clock ST is comapred with the phase of the received data SD. The phase change quantity supervisory section 12 consists of a supervisory device 121, supervises the change of the phase of the clock ST and the data SD and raises alarm when a prescribed change is exceeded. Thus, the clock mode setting error is detected quickly and easily.


Inventors:
NAKAMURA MASARU
Application Number:
JP6878486A
Publication Date:
October 05, 1987
Filing Date:
March 28, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L7/00; H04L25/40; (IPC1-7): H04L7/00; H04L25/40
Attorney, Agent or Firm:
Aoki Akira