To obtain a clock multiplying circuit which reduces power consumption and generates a multiplying clock signal with a correct duty ratio by suppressing the variation owing to an operation condition, such as temperature.

An inputted clock signal F and a delay clock signal delayed by a delay adjustment delay line 11 are inputted to an exclusive OR circuit 12 to take exclusive OR. A multiplying clock signal H according to the phase difference between the signals F and G is outputted from the circuit 12, electric charge is charged and discharged by a loop filter 13 to generate a delay quantity adjusting signal, to adjust the delay quantity of the line 11.