To provide a clock output circuit suitable for a PLL circuit or the like to prevent the generation of a narrow pulse when an oscillation mode is shifted to a power-down mode.

This clock output circuit is provided with an oscillating part 1 which stops an oscillation output when an oscillation mode is shifted to a power-down mode based on a signal to instruct power-down, a power-down time output fixing part 4 which outputs the oscillation output from the oscillating part 1 as a clock output in the oscillation mode, and fixes the clock output to a specified logical level in the power-down mode and a power-down permitting part 3 which shifts the oscillating part 1 to the power-down mode when a signal to instruct the power-down is inputted after the clock output is changed to the logical level specified in the power-down mode otherwise.

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