PURPOSE: To automatically optimize a clock supplied to each digital signal processing circuit by omitting the work of adjusting the phase of the clock for each digital signal processing circuit by using a delay circuit.

CONSTITUTION: A digital signal B being a test pattern signal and a clock D are phase-compared by a phase comparator circuit 6, and the phase difference output is smoothed by a smoothing circuit 7. Then, the output of the smoothing circuit 7 is converted into a digital signal by an A/D conversion circuit 8, and a phase adjusting circuit 10 is controlled. The phase adjusting circuit 10 operates phase control so that the phase of the clock D is matched with the phase of the digital signal B. Thus, the clock D whose phase is matched with the phase of the digital signal B can be obtained.