To eliminate delay at the re-addition through triple gate steps by cutting an electric high-volt (H) signal on AB=11 digits with an intermediate 00 low-volt (L) signal.

Signals C and H on AB=11 of start point (s) digit and one digit of AND gate are passed through a Cts line 2, diode di3 and intersection p4 and inputted to an AND gate 5 of terminal (t) digit, AND gate 6 and NOR gate 7 and the outputs of respective gates 5 to 7 are sent to an OR gate 8. They are returned from a (p) point 4 through a resistor r9 to a (q) point 10 on the Cts line 2, a line is extended downward from the (p) point 4 and linked with the output point of a NAND gate 11, and the 00 L signal prepared by AB=11 of intermediate (s+1) to (t-1) digits and OR gate 12 is inputted through a di13 to the Cts line 2. An AND gate 14 and NOR gate 15 are provided on the lower step of respective digits, the output line of the AND gate 14 is inputted through a point e1 to the upper AND gate 5 and NOR gate 7, and the output line of the NOR gate 15 is inputted through a point e0 to the upper AND gate 6 and NOR gate 7.