Title:
CLOCK RECOVERY CIRCUIT
Document Type and Number:
Japanese Patent JP3212385
Kind Code:
B2
Abstract:
PURPOSE: To detect a data conversion point of reception data efficiently with simple configuration by providing an offset circuit offsetting a phase angle signal of an output of a demodulator by a prescribed angle.
CONSTITUTION: An offset circuit 3 offsets a phase angle signal θ of an output of a demodulator 100 by a prescribed angle. An edge detection circuit 4 detects a prescribed data conversion point of reception data based on an output θs of the offset circuit 3. A phase comparator circuit 5 compares a phase of the data conversion point detected by the edge detection circuit 4 with a phase of a recovered clock signal. A clock generating circuit 6 generates the recovered clock signal so as to make the phase difference constant based on the phase difference detected by the phase comparator circuit 5.
Inventors:
Hideto Furukawa
Koji Matsuyama
Tomoki Sato
Koji Matsuyama
Tomoki Sato
Application Number:
JP30368392A
Publication Date:
September 25, 2001
Filing Date:
November 13, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L7/027; H04L27/22; (IPC1-7): H04L27/22; H04L7/027
Domestic Patent References:
| JP440029A | ||||
| JP56134865A | ||||
| JP6152673A |
Other References:
１９９１年電子情報通信学会春季全国大会講演論文集 分冊２，島方幸広 大沢英男”ＰＳＫベースバンド遅延検波復調器の構成と特性”ｐ．２−３６０
Attorney, Agent or Firm:
▲高▼須 宏